Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors


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International Journal on Smart Sensing and Intelligent Systems

Subject: Computational Science & Engineering, Engineering, Electrical & Electronic


eISSN: 1178-5608




VOLUME 4 , ISSUE 2 (June 2011) > List of articles

Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors

P. Saha / A. Banerjee / A. Dandapat / P. Bhattacharyya *

Keywords : Vedic Formulae, Multiplication, High Speed, Low Power, Latency.

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 4, Issue 2, Pages 268-284, DOI:

License : (CC BY-NC-ND 4.0)

Received Date : 09-May-2011 / Accepted: 25-May-2011 / Published Online: 01-June-2011



Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formulae). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high speed low power processor is reported in this paper. Simple Boolean logic is combined with ‘Vedic’ formulas, which reduces the partial products and sums generated in one step, reduces the carry propagation from LSB to MSB. The implementation methodology ensure substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Booth Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting 32×32 multiplier was only ~1.06 us and consumes ~132 uW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones.

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